Conventional system architecture for a Sonet/SDH system has a number of disadvantages including excessive number of logic devices, redundant processing operations, and inefficient use of memory. FIG. 1 illustrates a system architecture for a Sonet/SDH system in accordance with the prior art.
Egress Pointer Movements
An inefficient aspect of the system architecture shown in FIG. 1 is the conventional egress pointer smoothing scheme employed. When performing high order pointer processing of a SDH/Sonet frame, the presence of 3 bytes of section overhead at the start of each row of 87 payload bytes, can result in uneven pointer adjustments as the phase of line and local frame change. At the output of the elastic store there is circuitry which is generating a solid SDH frame structure which is aligned to the system clock, which has spaces in it for customer data which haven't been used as yet. Every time one of those spaces comes up the elastic store reads a byte of customer data which has been written into it by the labeler and passes it on to the point of generation block and out of the system. So if everything in the network is synchronized what will happen is the labeler will be writing one byte in at the same rate the high order pointer, or the elastic store, is writing one byte out to the rest of the network. However, due to frequency differences this is not always the case. The pointer generator checks each of the FIFOs of the elastic store, in turn, to determine if that FIFO is at or near a full threshold or an empty threshold. If either condition exists, the pointer generator will perform a pointer increment or decrement, respectively, which adds a byte into the payload or deletes a byte from the payload.
The determination is made at a precise spot within the frame, however the section overhead could be rolling past this sampling point. The sampling point is a fixed position in the outgoing frame, but the incoming frame can be moving relative to that. So as the section overhead goes past nothing is written in, but data is still being read out. The elastic store appears to empty quite quickly and pointers will be written erratically (either a burst of pointers or none) during this time. This erratic behavior may appear to change the frequency at which the customer data is arriving over a very short period or may cause bit errors.
This behavior is undesirable, and various techniques have been adopted to smooth the egress pointer adjustments.
Marking Synchronization Positions in the Elastic Store
Conventional methods of signaling the position of the synchronization bytes in the elastic store either use memory inefficiently or unduly increase system complexity. A high or low order elastic store in a SDH/Sonet system requires one byte in each frame of data to be marked for synchronization purposes. Conventionally this is the J1 byte for High Order traffic, and the V5 byte for low order traffic. This is normally achieved by adding one bit to the byte in the elastic store, and setting this bit high only when the associated byte contains the appropriate byte. This increases the width of the required memory by 1 bit. Good design practice also requires that a 1 bit parity signal is calculated for each traffic byte, and passed through the system for error checking. These two requirements mean that a conventional elastic store memory would need to be 10 bits wide (8 data bits, 1 parity bit, one flag bit). Typical memories in FPGAs are 9 or 18 bits wide. Thus a 10 bit word will need an 18 bit memory, and will use twice the memory resource that would be needed if it could be implemented using a 9 bit memory.
This disadvantage has been addressed in various ways in the prior art. When implementing ASIC designs, the designer can typically generate memories of any word width, so the need for 10 bit memories is not restrictive. In FPGA designs, the designer has the option of terminating parity on the input of the Elastic Store, and regeneration in on the output. This means that parity protection is not complete within the device, which is undesirable.
Another technique known to be used is to deliberately introduce a parity error on the byte to be labeled. Since these occur on a regular basis, and circuit on the output of the elastic store can verify that these occur when expected, and reset the deliberate changes back to their true state. Implementing this function adds significant design complexity. 10 bit RAMs are inefficient in FPGA implementations. Inverting the parity bit adds significant complexity, and can result in false diagnostic error reports within the device.
Overhead and Pointer Processing
A further disadvantage of the conventional system architecture is overhead and pointer processing. The overhead and pointer processing blocks of a SDH/Sonet system are conventionally directly coupled to the traffic path. In order to achieve high traffic throughput, a typical ASIC or FPGA will implement several traffic paths (or lanes) in parallel. Each lane will carry a portion of the overall traffic. Each lane in a high bandwidth device will contain all the logic associated with processing pointers and overhead associated with that lane. This occupies a large number of gates, but is used for only a small fraction of the payload. That is, the actual gates within the design dedicated to a particular lane are only being used 3-5% of the time, and when those gates aren't being used, identical gates in other lanes are being used.